The present invention relates to a current source device which is used in a semiconductor integrated circuit or the like and particularly suitable for the supply of light-emission drive currents to a plurality of light-emitting elements in an image display device in which the light-emitting elements are disposed and configured in matrix form.
FIG. 1 is a block diagram showing a schematic configuration of an image display device that uses general organic electroluminescence (hereinafter called “organic EL”). As shown in the same figure, n data lines A1 through An and m scan lines B1 through Bm arranged so as to intersect therewith are formed in a display panel 4. Organic EL elements E1,1 through Em,n that assume pixels are formed at portions where the data lines and the scan lines intersect one another. That is, an image to be displayed is configured by light emission of the m×n organic EL elements formed on a display panel.
The scan lines B1 through Bm are connected to a scan line drive unit 2 including scan line switches SWB1 through SWBm. With the switching operations of the scan line switches, a ground potential or a predetermined positive potential VH (e.g., 10V) is applied to the respective scan lines. The scan line switches SWB1 through SWBm sequentially apply the ground potential to the scan lines in accordance with a control signal supplied from a controller 1. Namely, the ground potential is sequentially applied to the scan lines at predetermined time intervals. Such periods are defined as scan line selection periods.
On the other hand, the data lines A1 through An are connected to a data line drive unit 3 including current sources J1 through Jn for generating drive currents to be supplied to the data lines, and data line switches SWA1 through SWAn. With the switching operations of the data line switches, the data lines are connected to either the current sources J1 through Jn or the ground potential. The data line switches SWA1 through SWAn selectively connect the data lines A1 through An to the current sources in sync with the scan line selection periods in accordance with a control signal supplied from the controller 1. Of the organic EL elements on the scan lines selected by the scan line switches, those connected to the current sources by the data line switches are supplied with light-emission drive currents from the current sources and emit light at luminances corresponding to the light-emission drive currents.
In FIG. 1, for example, the scan line B1 is selected by being connected to the ground potential by the scan line switch SWB1, and the data lines A2 and A3 are connected to their corresponding current sources J2 and J3 by the data line switches SWA2 and SWA3. Thus, the organic EL elements E1,2 and EL1,3 provided at the portions where the scan line B1 and the data lines A2 and A3 intersect, are respectively supplied with light-emission drive currents from the current sources J2 and J3 and emit light at luminances corresponding to the light-emission drive currents. All the scan lines B1 through Bm are sequentially selected within a predetermined frame period. In sync with it, light-emission drive currents corresponding to luminances are supplied to their corresponding organic EL elements, which in turn emit light thereby to form one screen.
FIG. 2 is an equivalent circuit diagram of a current source device that constitute the current sources J1 through Jn for supplying the light-emission drive currents to the respective organic EL elements via the data lines A1 through An in the above image display device. The current source device comprises a single gate voltage supply unit 10 and an output unit 20 comprising n current output circuits 30-1 through 30-n respectively corresponding to the data lines A1 through An.
The gate voltage supply unit 10 comprises an operational amplifier OP1, PMOS transistors P1 and P2 and a resistor R1. An inversion input terminal of the operational amplifier OP1 is supplied with a predetermined reference voltage V1. The output of the operational amplifier OP1 is connected to the gate of the PMOS transistor P2. The source of the PMOS transistor P2 is connected to the drain of the PMOS transistor P1, and the drain thereof is connected to the resistor R1 whose one end is fixed to a predetermined negative-side potential Vss. The potential of a connecting point of the PMOS transistor P2 and the resistor R1 is supplied to a non-inversion input terminal of the operational amplifier OP1. The gate of the PMOS transistor P1 is fixed to the negative-side potential Vss and a source voltage Vdd is applied to the source thereof. In the gate voltage supply unit 10 having such a configuration, the gate voltage of the PMOS transistor P2 is controlled by the output of the operational amplifier OP1, so that a reference current I1 corresponding to the reference voltage V1 flows through a current path routed through the PMOS transistors P1 and P2 and the resistor R1. Incidentally, since the PMOS transistor P1 has a predetermined on resistance while it is always in an ON state, the PMOS transistor P1 functions as a resistive element.
The output unit 20 comprises current output circuits 30-1 through 30-n corresponding to the data lines A1 through An as described above. The current output circuits 30-1 through 30-n respectively have the same configuration. In each of the current output circuits, a PMOS transistor P4 has a gate connected to a gate line of the PMOS transistor P2, i.e., an output line of the operational amplifier OP1 and functions as a current output FET for generating an output current to be supplied to the corresponding data line. That is, the gate of the PMOS transistor P4 is supplied with a common gate voltage in each current output circuit. The drain of the PMOS transistor P4 is connected to the drain of an NMOS transistor N1 and the source thereof is connected to the drain of a PMOS transistor P3. The source of the NMOS transistor N1 is fixed to the negative-side potential Vss and the gate thereof is supplied with a control signal NSW from a controller 1. Output terminals OUT1 through OUTn are provided at connecting points of the PMOS transistors P4 and the NMOS transistors N1, and the data lines A1 through An are connected to their corresponding output terminals OUT1 through OUTn. The source voltage Vdd is applied to the source of each PMOS transistor P3 and the gate thereof is supplied with a control signal PSW from the controller 1. By setting the dimensions (ratios W/L between gate widths and gate lengths) of the PMOS transistors P2 and P4 and the PMOS transistors P1 and P3 identical to each other in the current source device having such a configuration, output currents each indicative of the same current value as that of the reference current I1 can be obtained from the output terminals OUT1 through OUTn, whereby light-emission drive currents can be uniformly supplied to the data lines A1 through An.
The PMOS transistors P3 and NMOS transistors N1 respectively correspond to the data line switches SWA1 through SWAn that switch whether the output currents should be supplied to their corresponding data lines. When the gate of each PMOS transistor P3 is supplied with a control signal of a Low level and the gate of each NMOS transistor N1 is supplied with a control signal of a Low level, the PMOS transistor P3 is brought to an ON state and the NMOS transistor N1 is brought to an OFF state. Thus, the potential of the corresponding output terminal is brought to a High level so that the corresponding data line is supplied with a light-emission drive current. On the other hand, when the gate of the PMOS transistor P3 is supplied with a control signal of a High level and the gate of the NMOS transistor N1 is supplied with a control signal of a High level, the PMOS transistor P3 is brought to an OFF state and the NMOS transistor N1 is brought to an ON state. Thus, the potential of the corresponding output terminal is brought to a Low level so that the supply of current to the corresponding data line is stopped. That is, the PMOS transistor P3 and the NMOS transistor N1 respectively constitute a positive-side (high side) switch and a negative-side (low side) switch respectively connected to the electric source and the negative-side potential with the PMOS transistor P4 functioning as the current output FET being interposed therebetween. A switching current path is formed by switching ON/OFF of the supply of current to each data line by these high side and low side switches. ON/OFF control on the output currents of the current source device is done every current output circuits 30-1 through 30-n, and the supply of light-emission drive currents and their supply stop are controlled every data line.
The current source device used in the organic EL image display device having the above-described configuration has been described in, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2003-131617).
FIG. 3 shows operation waveforms of the respective parts in the current source device having the above-described conventional configuration at the time that the supply of an output current is caused to continue at the nth current output circuit 30-n from a state in which all the current source circuits 30-1 through 30-n supply output currents to the respective data lines, and the current supply is transitioned to its stop state at the 1st through n−1th current output circuits other than the above. In such a case, the control signals PSW and NSW are both switched from a Low level to a High level with the timings provided to stop the supply of currents to the data lines at the 1st through n−1th current output circuits. On the other hand, the control signals PSW and NSW are maintained at the Low level at the nth current output circuit 30-n to maintain the current supply. Incidentally, the control on the input of such control signals PSW and NSW is conducted by the controller 1 based on image data.
Here, parasitic capacitances C1 respectively exist between the gates and drains of the PMOS transistors P4 of the current output circuits 30-1 through 30-n, and a combined capacitance as viewed from the output of the operational amplifier OP1 assumes n*C1. Namely, a large-capacity capacitor can be assumed to be connected to the output line of the operational amplifier OP1. When, in this case, the respective NMOS transistors N1 of the 1st through n−1th current output circuits are respectively brought to an ON state in unison according to the switching of the control signal NSW, a charging current flows through the parasitic capacitances C1 in unison. As the charge into each parasitic capacitance C1 takes place in a short period of time, the instantaneous value of the charging current increases. When the drive capacity of the operational amplifier OP1 is low, the potential of the output line of the operational amplifier OP1 is reduced primarily during a charging period as shown in FIG. 3. When the potential of the output line of the operational amplifier OP1 is reduced primarily, the gate voltage of the PMOS transistor P4 controlled to output a predetermined constant current is reduced at the current output circuit 30-n to cause the current supply to continue. Therefore, a malfunction occurs in which the output current rises beyond a predetermined control value occurs. As a result, a problem arises in that the light-emission drive current increased due to the malfunction is temporarily supplied to each organic EL element connected to the data line An, thereby exerting an effect on light-emission luminance.